Digital Logic Simulator
Connect binary logic gates and D flip-flops to see how a circuit responds to a discrete input sequence. Gates evaluate in dependency order; each flip-flop samples its D input at a rising primary-input clock edge, and all Q outputs update simultaneously. The displayed outputs are recomputed after that edge. This is an ideal 0/1 teaching model, without propagation delay, unknown levels, analog voltages or hardware timing guarantees.
Key features
- Eight real binary gate functions: AND, OR, XOR, NAND, NOR, XNOR, NOT and buffer
- Gate dependency sorting with missing pin, unknown wire and combinational loop rejection
- Rising-edge D flip-flops that sample pre-edge D and update Q simultaneously
- Editable primary-input 0/1 sequence of up to 64 ticks, with initial clock level assumed low
- Per-tick trace table and downloadable SVG waveform with input, gate, Q and output lanes
- Strict, bounded local JSON circuit import, export and deterministic round-trip
How to use
- Start from the ENABLE/XOR flip-flop example or add primary inputs, gates, flip-flops and outputs.
- Choose each gate type and connect its input pins to a primary input, another gate or a flip-flop Q. Connect every D pin; choose a primary input for each CLK pin.
- Set 0 or 1 for every primary input at every tick, adding or removing ticks as needed. The clock begins conceptually at 0 before tick 0.
- Run the circuit. Inspect the pre-edge D sample, rising-edge markers, after-edge Q state and resulting outputs in the trace table and waveform.
- Download the SVG waveform and full circuit JSON. Paste or open a saved JSON file to restore the gates, wires, initial state and sequence.
Use cases
- Check all four rows of a basic gate truth table
- Teach why a D flip-flop updates only on a 0→1 clock transition
- Explore safe feedback through stored Q versus an invalid combinational cycle
- Share a small reproducible 0/1 circuit and input sequence as JSON
Frequently asked questions
When does a D flip-flop update?
At a tick whose primary-input CLK is 1 after being 0 on the previous tick. Each D value is computed with the previous Q state before the edge; all triggered Q outputs update together. Clock is assumed low before the first tick, so a high first sample is a rising edge.
Why is a gate loop rejected but Q feedback allowed?
Gate-to-gate cycles have no defined stable value in this zero-delay binary model, so they fail before simulation. A path through a D flip-flop Q is broken by stored state and can be evaluated one tick at a time.
Can a flip-flop clock come from another gate?
No. For an unambiguous discrete sample model, each CLK pin must connect directly to a primary input. Derived or asynchronous clocks, propagation delays, setup/hold times and metastability are outside this tool.
What happens if a pin is blank or a wire refers to a removed node?
The circuit fails validation with a pin or wire error. It never silently treats an unconnected signal as zero. Duplicate IDs, extra/missing sequence bits and combinational cycles also fail.
Is the circuit suitable for physical electronics design?
No. Logic is strictly two-state 0/1, one discrete row per tick. There are no X/Z values, voltage thresholds, fan-out, delays, glitches or electrical safety checks.
Are my circuit files uploaded?
No. Validation, simulation, waveform generation and JSON downloads run locally in this browser tab.
Privacy
Circuit wiring and sequence stay in this browser tab. A JSON or SVG file is downloaded only when you request it; no circuit data is submitted to a server API.
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